Some low to medium power Integrated Circuit devices (ICs), i.e. ICs operating at low to medium output power ranging between 2 Watts DC and 10 Watts DC peak, are known to incorporate a combination of CMOS, bipolar, and vertical drain MOS (VDMOS) and/or lateral drain MOS (LDMOS) power transistor devices on the same substrate.
The power LDMOS device is becoming the preferred structure due to the excellent characteristics of the LDMOS for low voltage applications (e.g. less than 1000 Volts), such as those required in the automotive electronics industry. For example, such power MOSFETs exhibit improved thermal stability, switching speed, and input impedance. The drain-to-source on-resistance (Rdson) is in the range of less than 1 mΩ-cm2. In addition, the voltage capability of the LDMOS can be layout adjustable (source-drain minimum space rule), and also as a result of the availability of advanced lithography techniques, the size of the LDMOS device can be reduced without changing the structure of the device.
However, in a lateral LDMOS transistor device, the voltage capability of the device is determined primarily by the resistivity of the epitaxial layer, which is a function of the doping concentration in the epitaxial layer, and the lateral length of the drift region, which is the region between the coplanar source and drain regions. The lateral length of the drift region cannot be less than a minimum value and the doping concentration cannot be above a maximum value in order to sustain the maximum operating voltage (Max BVdss) of the device. Thus, even with the usage of more advanced lithography techniques, for example in 0.8 μm and 0.6 μm design rule specifications, the lateral length of the drift region cannot go below the minimum value. In LDMOS the reduction of Rdson is limited due to the requirement of high breakdown voltage BVdss of these devices, which relatively thick and low doped epitaxial drift region governed by the “silicon limit” property expressed in the equation Rdson,sp=8.3×10−9(BVdss)2.5(mΩ-cm2).
Attempts have been made to reduce the Rdson in MOSFETs, however, it is desirable for the drain-to-source on resistance Rdson to be as small as possible so that the drain-to-source voltage and hence the power dissipation is low as possible. Additionally, the surface area of the LDMOS device accounts typically for 30% to 70% of the total area of the combination IC. Thus, with a LDMOS transistor device having a minimum lateral length for the drift region, the area of the LDMOS device can limit the overall die size reduction and hence is a major limiting factor for the overall industry to further reduce costs and improve the performance of such combination ICs.
Thus, there is therefore a need for an improved lateral semiconductor device which allows for further Rdson reduction enhancing BVdss without die size expansion.